This invention relates generally to a method and structure for preventing of unwanted wet etchant penetration at the interface region between photoresist material and underlying masked metal area when an adjacent area of unmasked exposed metal is being etched.
In the processing of circuit boards according to one conventional technique, a copper plate or layer is provided on one or both sides of an underlying substrate. The copper is patterned by photoresist and etch techniques to form the desired line and pad patterns prior to subsequent fabrication of the completed printed circuit board. One conventional technique for providing the desired line and pad pattern on the copper layer is by photolithographic technology. In this technology a photoresist material is applied over the exposed copper layer and then patternwise exposed to actinic radiation and developed to delineate the desired pattern in the photoresist. The photoresist can be either negative or positive resist as is well known in the art. Following the exposure and development, the desired pattern is transferred to the underlying copper below the developed and dissolved photoresist. The copper remaining underneath the undissolved and hence remaining photoresist defines the ultimately desired pattern of wires and pads. Following the developing of the photoresist, the revealed underlying copper is etched to remove it thereby leaving the masked copper adhering to the substrate. This is conventional prior art technology.
In forming the copper layer or plates on a substrate, one conventional prior art practice is to use planishing plates which are highly polished and extremely smooth as interface plates when the substrates with the copper layers are being formed. Such a technique is described in the prior art section of U.S. Pat. No. 3,969,177. This patent describes the prior art technique of utilizing planishing plates in the process of fabricating the printed circuit panels. As described in this patent, it is necessary to have a relatively flat surface to provide for proper adherence of the thin film photoresist. Further, as described in this patent, the use of planishing plates has several drawbacks including dimensional instability of the laminated panels. Also, when planishing plates are used and reused the plates tend to get nicked and scarred which will result in the plates leaving an impression on the surface of the copper; and, additionally when they are used and reused even under reasonably clean conditions specks of material can be found to be adhering to the surface of the planishing plates which will also cause surface irregularities in the copper plate and leave traces of epoxy on the surface.
U.S. Pat. No. 3,969,177 describes a technique wherein partially cured cores with copper plates thereon are used in place of planishing plates, and circuit boards are formed using copper to copper plate contact in place of a planishing plate against the copper. As described therein, a reasonably smooth surface is provided by this manner. However, even this surface which while reasonably smooth still is a matte finish and has a peak to valley roughness of up to 0.2 mils. This degree of surface roughness or degree of matte finish is acceptable in many application wherein photoresist technology is utilized. However, as advancing technology allows smaller and smaller lines to be formed and narrower spacing between lines to be accomplished, even this surface roughness in many instances, is significant enough that when using certain conventional dry photoresist techniques the wet etchant penetration is significant enough to provide an unacceptably high number of shorts and opens in the location adjacent to those areas where the copper has been etched.
While smoother copper surfaces could be provided by the use of planishing plates, i.e. a smoother overall surface would be provided, nevertheless, the planishing plates still have the significant drawbacks as noted above.